1. Field of the Invention
The present invention relates to a data shifting circuit, and particularly to a data shifting circuit capable of realizing various shifting functions and rotating functions by utilizing a MOS barrel shifter.
2. Description of the Related Art
FIG. 1 is a block diagram showing an example of conventional configuration of a date shifting circuit for processing 4-bit data by utilizing a MOS barrel shifter.
In FIG. 1, numeral 3 designates a first bus for inputting 4-bit data to be processed from the outside, respective bits are inputted to a MOS transistor array 8, to be described later, in order from the higher bits respectively through bit lines 3a, 3b, 3c and 3d.
Numeral 4 designates a second bus for inputting an optional value for compensating the data, the bits, except the lowest bit, are inputted to the MOS transistor array 8, to be described later, in order from the higher bits respectively through bit lines 4a, 4b and 4c.
Numeral 6 designates a shift quantity bus to which a signal (shift quantity signal) indicating a shift, quantity is inputted. The shift quantity bus 6 is connected to a decoder 7. The decoder 7 signifies any of 0-bit shift line 7a, 1-bit shift line 7b, 2-bit shift line 7c and 3-bit shift line 7d corresponding to the shift quantity signal, by decoding the shift, quantity signal.
Numeral 9 designates an output bus for outputting the data to the outside from the MOS transistor array 8, respective bits are outputted in order from the higher bits from the MOS transistor array 8 through signal lines 9a, 9b, 9c and 9d.
The MOS transistor array 8 is constituted by 16 MOS transistors 8aa, 8ab, . . . 8dc and 8dd. Specifically, the MOS transistor array 8 is arranged in a matrix of 4 rows.times.4 columns, wherein to drains of the MOS transistors 8aa, 8ba, 8ca and 8da arranged in the row direction, the bit line 9a of the output bus 9 is connected, to drains of the MOS transistors 8ab, 8bb, 8cb and 8db, the bit line 9b of the output bus 9 is connected, to drains of the MOS transistors 8ac, 8bc, 8cc and 8dc, the bit line 9c of the output bus 9 is connected, and to drains of the MOS transistors 8ad, 8bd, 8cd and 8dd, the bit line 9d of the output bus 9 is connected. To gates of the MOS transistors 8aa, 8ab, 8ac and 8dd arranged in the column direction, the shift line 7a is connected, to gates of the MOS transistors 8ba, 8bb, 8bc and 8bd, shift line 7b is connected, to gates of the MOS transistors 8ca, 8cb, 8cc and 8cd, the shift line 7c is connected, and to gates of the MOS transistors 8da, 8db, 8dc and 8dd, the shift line 7d is connected.
Furthermore, to sources of the MOS transistors in the MOS transistor array 8, the 4-bit lines 3a, 3b, 3c and 3d of the first bus 3 and the bit lines 4a, 4b and 4c, except the lowest bit 4d, of the second bus 4 are connected in a step-like fashion.
Specifically, the bit line 3a of the first bus 3 is connected to the source of the MOS transistor 8aa, the bit line 3b to the sources of the MOS transistors 8ba, 8ab, the bit line 3c to the sources of the MOS transistors 8ca, 8bb, 8ac, the bit line 3d to the sources of the MOS transistors 8da, 8cb, 8bc, 8ab, and the bit line 4a of the second bus 4 is connected to sources of the MOS transistor 8bd, 8cc, 8db, the bit line 4b to sources of the MOS transistors 8cd, 8dc, and the bit line 4c to a source of the MOS transistor 8dd.
Next, the operation of the conventional data shifting circuit utilizing the MOS barrel shifter shown in FIG. 1 is described.
For example, in case of 3-bit left shift of 4-bit data "1001", the data "1001" is inputted to the first bus 3 and all bits of the second bus 4 are set to "0". Also, a signal indicating a shift quantity "3" is given to the shift quantity bus 6, and decoded by the decoder 7 to select the shift line 7d for 3-bit shift.
Thereby, the MOS transistors 8da, 8db, 8dc and 8dd, to whose gates the shift line 7d in the MOS transistor array 8 is connected, are turned ON and the other MOS transistors are turned OFF, so that output; data "1000" is outputted from the output bus 9.
Next, the case of rotating the data is described.
Hereupon, the left n-bit rotation of m-bit data means to shift the data to the left by n bits, and to add higher n-bit data which has been overflown from the m bits being a data bit width, as the result of shifting the data to the left by n bits, and the m-bit data which has been shifted to the left by n bits.
For example, in case of 3-bit rotation of 4-bit data "1001", the data "1001" which is inputted to both the first bus 3 and the second bus 4. Also, the signal indicating the shift quantity "3" is given to the shift quantity bus 6 and decoded by the decoder 7 to select the shift lien 7d for 3-bit, shift.
Thereby, the MOS transistor 8da, 8db, 8dc, 8dd, to whose gates the shift line 7d is connected, in the MOS transistor array 8 are turned ON, and the other MOS transistors are turned OFF, so that output data "1100" is outputted from the output bus 9.
In the conventional data shifting circuit as described above, though the left shift or rotation is possible, for executing the right shift or rotation, another barrel shifter, in which connections of the first bus 3 and the second bus 4 of the barrel shifter shown in FIG. 1 are changed, is necessary.
And hence, in case of providing the both barrel shifters in a 1-chip microcomputer and the like, a circuit configuration becomes complicated and the number of MOS transistors increases to occupy a large area on the chip.